Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device comprising:
a device area formed on a semiconductor substrate consisting of a gate insulating film, source.multidot.drain areas and a gate electrode; and a device separation area composed of a thick insulating film, a first thin insulating film with film thickness almost equal to that of the gate insulating film and a first high-concentration impurity layer provided under the first thin insulating film.
Description of the Related Art
When an MOS transistor receives ionizing radiation such as gamma rays, the increase in accumulation of the fixed positive charge in a silicon oxide film and increase of the interface state density of the interface between the oxide film and silicon cause deterioration of the characteristics of the MOS transistor such as threshold voltage shifts or increase in leakage current. It is known that the thicker the oxide film, the more the amount of accumulation of the fixed positive charge. Therefore, an inversion layer caused by an electric field of fixed positive charge more readily forms on the surface of a P-type semiconductor substrate placed under a thick field oxide film than for a case in which the substrate is placed under a thin gate oxide film. Leakage currents that flow between a source and a drain under the end portion of the gate of an NMOS transistor, leakage currents between adjacent NMOS transistors, or leakage currents between an NMOS transistor and an N-well are caused by parasitic transistors which form through the thick field oxide film. This causes serious problems for the semiconductor devices to be used in a space environment.
Of these types of leakage currents, the prevention of the leakage currents that flow between the source and drain under the end portion of a gate is attempted in a semiconductor device having the structure shown in FIGS. 1a, 1b, 1c and 1d (Japanese Patent Laid-open No. 87-250671). Here, FIG. 1a is a view showing a plan of a conventional example of an NMOS transistor, and FIGS. 1b, 1c and 1d are sectional views taken along line B--B, line C--C and line D--D, respectively, of FIG. 1a. The conventional example of the NMOS transistor will be described below with reference to these drawings.
On the surface of a P-type semiconductor substrate 21, there are provided field oxide films 22, 23 and 24 (represented by hatched portions in FIG. 1a). On the surface of the substrate 21 within a device area enclosed by the field oxide films 23 and 24, a thin gate oxide film 25 is formed. An oxide film 26 having film thickness equal to that of the gate oxide film 25 is formed between the field oxide films 22 and 23, and another similar oxide film 26 is also formed between the field oxide films 22 and 24. A gate electrode 27 is formed in such a way that both ends reach the oxide films 26, and under the end portions of the gate electrode 27, a thin oxide film 28 having the same film thickness as the gate oxide film is provided so as to connect the oxide films 25 and 26. Within the area enclosed by the field oxide films 23 and 24, N.sup.+ -type source-drain areas 29, 30 are formed using the gate electrode 27 as a mask of ion implantation. Further, under the oxide film 26, a P.sup.++ -type high-concentration impurity layer 31 is formed in a self-aligned configuration with reference to the gate electrode 27.
With this conventional structure, since a thin oxide film 28 with the same thickness as gate oxide film 25 is provided under the gate electrode 27, it is possible to suppress the increase of the leakage current which is caused by radiation generated between the source-drain areas 29, 30 shown by arrows in FIG. 1a.
Further, when this conventional structure is applied to a CMOS transistor, latch-up phenomenon triggered by penetration of a high-energy particle can be limited by connecting the P.sup.++ -type high-concentration impurity layer 31 to a ground wire to get the same electric potential as source area 29 or 30,.
The above semiconductor device of the conventional structure exhibits sufficient resistance to radiation if the gate length of the transistor is relatively long, for example, if the gate length is approximately 2 .mu.m. However, if the above structure is applied to a recent device which has a gate length in the submicron range, the following problem occurs.
When the gate length of the device is short, and particularly when it is 1 .mu.m or less and this device is applied to realize the structure of FIGS. 1a, 1b, 1c, 1d, the field oxide films 23, 24 are disposed too close to each other on both ends of the oxide film 28. As a result, depletion layers or inversion layers, which are produced under the field oxide films 23, 24 by the accumulated fixed positive charge when the device is irradiated such as when used in space, form in an overlapping configuration, thereby causing leakage currents to flow between the source and drain as shown by arrows in FIG. 1a.